Invention Grant
US09594486B2 Processor architecture using a RISC processor and multiple adjunct processors
有权
使用RISC处理器和多个辅助处理器的处理器架构
- Patent Title: Processor architecture using a RISC processor and multiple adjunct processors
- Patent Title (中): 使用RISC处理器和多个辅助处理器的处理器架构
-
Application No.: US14547947Application Date: 2014-11-19
-
Publication No.: US09594486B2Publication Date: 2017-03-14
- Inventor: James Albert Luckett, Jr. , Chad Michael Rowlee , Shengli Fu
- Applicant: MYTH INNOVATIONS, INC.
- Applicant Address: US TX Dallas
- Assignee: MYTH INNOVATIONS, INC.
- Current Assignee: MYTH INNOVATIONS, INC.
- Current Assignee Address: US TX Dallas
- Agency: Jackson Walker LLP
- Agent Christopher J. Rourk
- Main IPC: G06F17/00
- IPC: G06F17/00 ; G06F3/0484 ; G09G5/377 ; G02B27/01 ; H04W12/04 ; G06F15/82 ; G06T1/20 ; H04L29/08 ; H04W12/08 ; G06F3/038 ; G06T19/00 ; H04W12/06 ; H04L29/06 ; H04W4/02 ; G06F3/147
Abstract:
A method for processing data comprising activating a reduced instruction set processor. Activating a basic input output system of the reduced instruction set processor. Activating a multiple boot loader of the reduced instruction set processor after the basic input output system has been activated. Activating a hardware abstraction layer of the reduced instruction set processor after the multiple boot loader has been activated. Activating a plurality of processors coupled to the reduced instruction set processor. Activating a common language infrastructure of the reduced instruction set processor. Synchronizing a dynamic link library of each of the plurality of processors with a common language infrastructure of the reduced instruction set processor.
Public/Granted literature
- US20150091923A1 PROCESSOR ARCHITECTURE USING A RISC PROCESSOR AND MULTIPLE ADJUNCT PROCESSORS Public/Granted day:2015-04-02
Information query
