A circuit layout data has a start value of a first-axis pitch and a start value of a second-axis pitch, the second axis pitch being transverse to the first-axis pitch. The start value of the first axis pitch and the start value of the second axis pitch correspond to single pattern lithography. The first axis pitch is scaled to a first axis single pattern-to-double pattern pitch transition threshold, and then additionally scaled until reaching a first axis double pattern resolution limit. Scaling the first axis pitch to the first axis double pattern resolution limit utilizes routing spaces parallel to the second axis pitch.