Invention Grant
- Patent Title: Method for semiconductor wafer alignment
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Application No.: US14297889Application Date: 2014-06-06
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Publication No.: US09601436B2Publication Date: 2017-03-21
- Inventor: Shing-Kuei Lai , Wei-Yueh Tseng , Hsiao-Yi Wang , De-Fang Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/268 ; G03F9/00 ; G03F7/20

Abstract:
A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices is formed on the active region. The semiconductor wafer also includes a wafer identification. The wafer identification is formed on the edge region and used for identifying the semiconductor wafer. The semiconductor wafer further includes an alignment mark. The alignment mark is formed on the edge region and is used for performing an alignment process of the semiconductor wafer.
Public/Granted literature
- US20150357287A1 METHOD FOR SEMICONDUCTOR WAFER ALIGNMENT Public/Granted day:2015-12-10
Information query
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