- 专利标题: Trie stage balancing for network address lookup
-
申请号: US14108581申请日: 2013-12-17
-
公开(公告)号: US09602407B2公开(公告)日: 2017-03-21
- 发明人: Zixiong Wang
- 申请人: Futurewei Technologies, Inc.
- 申请人地址: CN Shenzhen
- 专利权人: Huawei Technologies Co., Ltd.
- 当前专利权人: Huawei Technologies Co., Ltd.
- 当前专利权人地址: CN Shenzhen
- 代理机构: Conley Rose, P.C.
- 主分类号: H04L12/44
- IPC分类号: H04L12/44 ; H04L12/745 ; H04L12/743 ; H04L12/56
摘要:
A trie comprising a plurality of subtries may be balanced by storing, in a first memory stage, a first root that identifies a first subtrie of a trie and a second root that identifies a second subtrie, which is a direct or indirect child of the first subtrie. A plurality of network address prefixes representing vertexes in the plurality of subtries may be stored in at least one additional memory stage. As the first subtrie is located on a top subtrie level which may contain relatively fewer network address prefixes, promoting the second subtrie to the top subtrie level may help improve memory utilization. Further, looking up any received network address may have less memory access latency.
公开/授权文献
- US20150172191A1 Trie Stage Balancing for Network Address Lookup 公开/授权日:2015-06-18
信息查询