Invention Grant
- Patent Title: Memories utilizing hybrid error correcting code techniques
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Application No.: US13725298Application Date: 2012-12-21
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Publication No.: US09612901B2Publication Date: 2017-04-04
- Inventor: Joshua D. Ruggiero , James A. Coleman , Gary J. Lavelle
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10

Abstract:
Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory, a transaction indicator and an execution unit indicator, and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.
Public/Granted literature
- US20130262958A1 MEMORIES UTILIZING HYBRID ERROR CORRECTING CODE TECHNIQUES Public/Granted day:2013-10-03
Information query
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