Invention Grant
- Patent Title: Low capacitance interconnect structures and associated systems and methods
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Application No.: US14514936Application Date: 2014-10-15
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Publication No.: US09613864B2Publication Date: 2017-04-04
- Inventor: Jin Lu , Hongqi Li , Kevin Torek , Thy Tran , Alex Schrinsky
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L21/308 ; H01L21/311 ; H01L21/321

Abstract:
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
Public/Granted literature
- US20160111372A1 LOW CAPACITANCE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS Public/Granted day:2016-04-21
Information query
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