- Patent Title: Internal/external clock selection circuit and method of operation
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Application No.: US15181076Application Date: 2016-06-13
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Publication No.: US09614509B1Publication Date: 2017-04-04
- Inventor: Abdullah Ahmed
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Conley Rose, P.C.
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K5/15 ; H03B5/32 ; H03K5/00

Abstract:
A clock circuit includes an amplifier, an electrical supply, a feedback circuit, and a comparator. The amplifier has an input node and an output node that are coupled to a crystal to provide an internal clock signal on the output node at a specified frequency. The electrical supply source provides electrical power to the amplifier at a specified input voltage. The feedback circuit is coupled between the input node and the output node, and forms a low pass filter for attenuating the internally generated clock signal on the input node. The feedback circuit biases the input node at a direct current (DC) voltage level that is biased to be less than the specified input voltage. When an external clock signal is applied at the output node, the comparator generates a digital clock signal according to the external clock signal, and when no external clock signal is applied at the output, the comparator generates the digital clock signal according to the internal clock signal.
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