Invention Grant
- Patent Title: Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
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Application No.: US14087520Application Date: 2013-11-22
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Publication No.: US09620202B2Publication Date: 2017-04-11
- Inventor: Zhengang Chen , Erich F. Haratsch , Sundararajan Sankaranarayanan
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Smith Tempel Blaha LLC
- Agent Robert A. Blaha
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G11C11/56 ; G11C16/34 ; G11C16/26 ; G11C29/02 ; G11C7/14

Abstract:
Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations.
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