- 专利标题： Chip with I/O pads on peripheries and method making the same
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申请号： US14755492申请日： 2015-06-30
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公开(公告)号： US09633960B2公开(公告)日： 2017-04-25
- 发明人: Chi-Chou Lin , Zheng-Ping He
- 申请人： SunASIC Technologies, Inc.
- 申请人地址： TW New Taipei
- 专利权人： Sunasic Technologies Inc.
- 当前专利权人： Sunasic Technologies Inc.
- 当前专利权人地址： TW New Taipei
- 代理机构： Law Offices of Scott Warmuth
- 代理商 Che-Yang Chen
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L23/00 ; H01L23/31 ; H01L21/768 ; H01L21/78 ; G06F3/044
摘要：
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.
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