- 专利标题: Field effect transistor structure with abrupt source/drain junctions
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申请号: US12700637申请日: 2010-02-04
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公开(公告)号: US09640634B2公开(公告)日: 2017-05-02
- 发明人: Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
- 申请人: Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L29/66 ; H01L29/08 ; H01L29/10 ; H01L29/16 ; H01L29/161 ; H01L29/165 ; H01L29/417 ; H01L29/49 ; H01L29/78 ; H01L21/20
摘要:
Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.