Invention Grant
- Patent Title: System, method, and program for robust interference rejection combining
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Application No.: US14341563Application Date: 2014-07-25
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Publication No.: US09641294B2Publication Date: 2017-05-02
- Inventor: Rohit Umesh Nabar , Kedar Durgadas Shirali
- Applicant: CISCO TECHNOLOGY, INC.
- Applicant Address: US CA San Jose
- Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patent Capital Group
- Main IPC: H04L5/00
- IPC: H04L5/00 ; H04B1/7105 ; H04L25/02 ; H04B7/08
Abstract:
An apparatus includes an interference rejection combining module, at least partially implemented in hardware. The interference rejection combining module determines a covariance based on a Hermitian transpose of a signal received on a subcarrier of a symbol that is not a pilot symbol.
Public/Granted literature
- US20160028516A1 SYSTEM, METHOD, AND PROGRAM FOR ROBUST INTERFERENCE REJECTION COMBINING Public/Granted day:2016-01-28
Information query
