Invention Grant
- Patent Title: Memory device and manufacturing method thereof
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Application No.: US14630498Application Date: 2015-02-24
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Publication No.: US09647031B2Publication Date: 2017-05-09
- Inventor: Kiyohito Nishihara
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2014-205295 20141003
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H01L27/22 ; H01L21/768 ; H01L23/522 ; H01L27/24

Abstract:
A memory device includes a substrate, first and second wirings above the substrate, a third wiring above the first and second wirings, a fourth wiring above the third wiring, a first contact electrically connected between the first wiring and the fourth wiring, a first insulator on the first contact, and a second contact on the first insulator, the second contact being electrically connected between the second wiring and the third wiring. The first contact overlaps the second contact in a direction that is orthogonal to an upper surface of the substrate.
Public/Granted literature
- US20160099209A1 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-04-07
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