Invention Grant
- Patent Title: Integrated circuit layout design system and method
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Application No.: US14709885Application Date: 2015-05-12
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Publication No.: US09652580B2Publication Date: 2017-05-16
- Inventor: Taejoong Song , Jae-Ho Park , Sanghoon Baek , Giyoung Yang , Sang-Kyu Oh , Hyosig Won
- Applicant: Taejoong Song , Jae-Ho Park , Sanghoon Baek , Giyoung Yang , Sang-Kyu Oh , Hyosig Won
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2014-0133271 20141002
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.
Public/Granted literature
- US20160026749A1 INTEGRATED CIRCUIT LAYOUT DESIGN SYSTEM AND METHOD Public/Granted day:2016-01-28
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