Invention Grant
- Patent Title: S/D connection to individual channel layers in a nanosheet FET
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Application No.: US14919634Application Date: 2015-10-21
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Publication No.: US09653287B2Publication Date: 2017-05-16
- Inventor: Mark Rodder , Joon Hong , Jorge Kittl , Borna Obradovic
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/417 ; H01L29/786 ; H01L29/45 ; H01L29/66 ; H01L29/06 ; H01L21/285

Abstract:
A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.
Public/Granted literature
- US20160126310A1 S/D CONNECTION TO INDIVIDUAL CHANNEL LAYERS IN A NANOSHEET FET Public/Granted day:2016-05-05
Information query
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