Invention Grant
- Patent Title: Hybrid ETSOI structure to minimize noise coupling from TSV
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Application No.: US13800124Application Date: 2013-03-13
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Publication No.: US09653615B2Publication Date: 2017-05-16
- Inventor: Chung-Hsun Lin , Yu-Shiang Lin , Shih-Hsien Lo , Joel A. Silberman
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/786 ; H01L29/66 ; H01L29/06 ; H01L23/48 ; H01L21/84

Abstract:
In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.
Public/Granted literature
- US20140264593A1 Hybrid ETSOI Structure to Minimize Noise Coupling from TSV Public/Granted day:2014-09-18
Information query
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