Invention Grant
- Patent Title: Device including vertically aligned two-dimensional material
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Application No.: US14972873Application Date: 2015-12-17
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Publication No.: US09658186B2Publication Date: 2017-05-23
- Inventor: Kiyeon Yang , Changseung Lee , Namjeong Kim , Yeonhee Kim
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2015-0095361 20150703
- Main IPC: H01L29/00
- IPC: H01L29/00 ; G01N27/414 ; H01L21/02 ; H01L21/3065 ; H01L29/786

Abstract:
A transistor includes a substrate, a two-dimensional material including at least one layer that is substantially vertically aligned on the substrate such that an edge of the layer is on the substrate and the layer extends substantially vertical to the substrate, a source electrode and a drain electrode connected to opposite ends of the two-dimensional material, a gate insulation layer on the two-dimensional material between the source electrode and the drain electrode, and a gate electrode on the gate insulation layer. Each layer includes a semiconductor having a two-dimensional crystal structure.
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