Invention Grant
- Patent Title: System and technique for rasterizing circuit layout data
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Application No.: US14576388Application Date: 2014-12-19
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Publication No.: US09658538B2Publication Date: 2017-05-23
- Inventor: Pei-Yi Liu , Cheng-Chi Wu , Cheng-Hung Chen , Jyuh-Fuh Lin , Wen-Chuan Wang , Shy-Jay Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F7/20

Abstract:
A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.
Public/Granted literature
- US20160180005A1 SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA Public/Granted day:2016-06-23
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