Invention Grant
- Patent Title: Techniques for increasing instruction issue rate and reducing latency in an out-of order processor
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Application No.: US14448790Application Date: 2014-07-31
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Publication No.: US09658853B2Publication Date: 2017-05-23
- Inventor: Harry Barowski , Tim Niggemeier
- Applicant: GLOBALFOUNDRIES INC
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC
- Current Assignee: GLOBALFOUNDRIES INC
- Current Assignee Address: KY Grand Cayman
- Agency: Scully Scott Murphy and Presser
- Agent Frank Digiglio
- Priority: GB1313825.0 20130802
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F5/14

Abstract:
A technique for operating a processor includes storing a first result to a writeback buffer, in response to a first execution unit of the processor attempting to write the first result of a first completed instruction to a register file of the processor at a same processor time as a second execution unit of the processor is attempting to write a second result of a second completed instruction to the register file. The writeback buffer is positioned in a dataflow between the first execution unit and the register file. A buffer full indicator logic is used to detect that the writeback buffer is unavailable. A buffer unavailable signal is transmitted, from the buffer full indicator logic, in response to detecting the writeback buffer is unavailable. In response to receiving the buffer unavailable signal, a buffer retrieving logic writes the first result from the writeback buffer to the register file.
Public/Granted literature
- US20150039862A1 TECHNIQUES FOR INCREASING INSTRUCTION ISSUE RATE AND REDUCING LATENCY IN AN OUT-OF-ORDER PROCESSOR Public/Granted day:2015-02-05
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