Invention Grant
- Patent Title: Circuits and techniques including cascaded LDO regulation
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Application No.: US14713312Application Date: 2015-05-15
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Publication No.: US09665112B2Publication Date: 2017-05-30
- Inventor: Amit Kumar Singh , Nitish Kuttan , Sriram Ganesan
- Applicant: Analog Devices Global
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Global
- Current Assignee: Analog Devices Global
- Current Assignee Address: BM Hamilton
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G05F1/56
- IPC: G05F1/56

Abstract:
A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.
Public/Granted literature
- US20160334818A1 CIRCUITS AND TECHNIQUES INCLUDING CASCADED LDO REGULATION Public/Granted day:2016-11-17
Information query
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