Invention Grant
- Patent Title: Methods of forming wiring structures and methods of manufacturing semiconductor devices
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Application No.: US15048993Application Date: 2016-02-19
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Publication No.: US09666478B2Publication Date: 2017-05-30
- Inventor: Thomas Oszinda , Tae-Jin Yim , Sang-Hoon Ahn , Nae-In Lee
- Applicant: Thomas Oszinda , Tae-Jin Yim , Sang-Hoon Ahn , Nae-In Lee
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Priority: KR10-2015-0064764 20150508
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/768
Abstract:
In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.
Public/Granted literature
- US20160329242A1 METHODS OF FORMING WIRING STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES Public/Granted day:2016-11-10
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