Invention Grant
- Patent Title: Semiconductor device and electronic device
-
Application No.: US15232143Application Date: 2016-08-09
-
Publication No.: US09666606B2Publication Date: 2017-05-30
- Inventor: Takanori Matsuzaki , Tatsuya Onuki
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office
- Agent Eric J. Robinson
- Priority: JP2015-163532 20150821
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/12 ; H01L27/12 ; H01L29/786
Abstract:
Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.
Public/Granted literature
- US20170053946A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE Public/Granted day:2017-02-23
Information query
IPC分类:
