- Patent Title: Non-planar semiconductor structure with preserved isolation region
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Application No.: US14609105Application Date: 2015-01-29
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Publication No.: US09666709B2Publication Date: 2017-05-30
- Inventor: Xiaoli He , Yanxiang Liu , Jerome Ciavatti , Myung Hee Nam
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Wayne F. Reinke, Esq.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/10 ; H01L29/06 ; H01L29/08 ; H01L29/417 ; H01L29/66 ; H01L29/739 ; H01L21/033 ; H01L21/32

Abstract:
A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.
Public/Granted literature
- US20160225895A1 NON-PLANAR SEMICONDUCTOR STRUCTURE WITH PRESERVED ISOLATION REGION Public/Granted day:2016-08-04
Information query
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