Invention Grant
- Patent Title: NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages
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Application No.: US14314663Application Date: 2014-06-25
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Publication No.: US09672102B2Publication Date: 2017-06-06
- Inventor: Akira Goda , Pranav Kalavade , Charan Srinivasan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Thorpe North & Western, LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10

Abstract:
Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method includes applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method also includes determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.
Public/Granted literature
- US20150378815A1 NAND PRE-READ ERROR RECOVERY Public/Granted day:2015-12-31
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