- 专利标题: Method of patterning incorporating overlay error protection
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申请号: US14863991申请日: 2015-09-24
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公开(公告)号: US09673050B2公开(公告)日: 2017-06-06
- 发明人: Anton J. deVilliers , Jeffrey Smith
- 申请人: Tokyo Electron Limited
- 申请人地址: JP Tokyo
- 专利权人: Tokyo Electron Limited
- 当前专利权人: Tokyo Electron Limited
- 当前专利权人地址: JP Tokyo
- 主分类号: H01L21/311
- IPC分类号: H01L21/311 ; H01L21/033
摘要:
Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spacer to define a hard border between features to be patterned. Such a spacer is positioned underneath an overlying relief pattern so that a portion of the spacer is exposed and protecting an underlying layer. Techniques herein can be used for metallization, and, in particular, metallization of a first metal layer above electronic device contacts. More broadly, techniques herein can be used for any type of critical placement where one structure is extremely close to another structure, such as with sub-resolution dimensions.
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