- 专利标题: Adaptive equalization circuit, digital coherent receiver, and adaptive equalization method
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申请号: US15203004申请日: 2016-07-06
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公开(公告)号: US09680667B2公开(公告)日: 2017-06-13
- 发明人: Daisuke Sasaki , Kazuhiko Hatae , Tomoki Katou , Nobukazu Koizumi , Masato Oota , Yasuo Ohtomo , Manabu Yamazaki , Masashi Sato
- 申请人: FUJITSU LIMITED
- 申请人地址: JP Kawasaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki
- 代理机构: Staas & Halsey LLP
- 优先权: JP2015-137587 20150709
- 主分类号: H04L25/03
- IPC分类号: H04L25/03 ; H04B10/61 ; H04L25/02
摘要:
A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a setting value based on the second signal.
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