Invention Grant
- Patent Title: Systems and methods for providing dynamic cache extension in a multi-cluster heterogeneous processor architecture
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Application No.: US14595998Application Date: 2015-01-13
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Publication No.: US09697124B2Publication Date: 2017-07-04
- Inventor: Hee Jun Park , Krishna Vsssr Vanka , Sravan Kumar Ambapuram , Shirish Kumar Agarwal , Ashvinkumar Namjoshi , Harshad Bhutada
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Smith Tempel Blaha LLC
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F11/34 ; G06F9/48 ; G06F9/50 ; G06F12/084 ; G06F12/0806 ; G06F12/0842 ; G06F12/0811 ; G06F12/0831

Abstract:
A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
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