Invention Grant
- Patent Title: Multiplication of first and second operands using redundant representation
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Application No.: US14939469Application Date: 2015-11-12
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Publication No.: US09703531B2Publication Date: 2017-07-11
- Inventor: David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
- Applicant: ARM LIMITED
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F7/533
- IPC: G06F7/533 ; G06F7/544

Abstract:
A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.
Public/Granted literature
- US20170139677A1 MULTIPLICATION OF FIRST AND SECOND OPERANDS USING REDUNDANT REPRESENTATION Public/Granted day:2017-05-18
Information query
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