Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more shared word lines. In cases where a first vertical NAND string of the first set and a second vertical NAND string of the second set are both connected to selected bit lines and the same shared word line, selectivity of memory cells may be provided by applying different voltages to the first drain-side select line and the second drain-side select line.