In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.