A wireless communication device includes a processor, a memory unit capable of retaining data in a power saving state, a clock control unit configured to control when a clock is to be supplied to each pair of processor and memory, and a power control unit configured to control an amount of power to be supplied to the processor and the memory unit. In the power saving state, the clock control unit stops supplying the clock to the processor and the memory unit, and the power control unit reduces the amount of power supplied to the memory unit. When returning from the power saving state, the power control unit increases the amount of power supplied to the memory unit, and the clock control unit starts supplying the clock to the memory unit before starting to supply the clock to the processor.