Invention Grant
- Patent Title: Memory error detection system
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Application No.: US14975828Application Date: 2015-12-20
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Publication No.: US09727408B2Publication Date: 2017-08-08
- Inventor: Aarul Jain , Dirk Wendel
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Agent Charles E. Bergere
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G06F11/16 ; G06F11/08 ; G06F11/10

Abstract:
An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.
Public/Granted literature
- US20170177428A1 MEMORY ERROR DETECTION SYSTEM Public/Granted day:2017-06-22
Information query