Invention Grant
- Patent Title: Configuration structure and method of a block memory
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Application No.: US14772455Application Date: 2014-11-27
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Publication No.: US09727415B2Publication Date: 2017-08-08
- Inventor: Jia Geng , Yuanpeng Wang , Ping Fan
- Applicant: CAPITAL MICROELECTRONICS CO., LTD.
- Applicant Address: CN Beijing
- Assignee: CAPITAL MICROELECTRONICS CO., LTD.
- Current Assignee: CAPITAL MICROELECTRONICS CO., LTD.
- Current Assignee Address: CN Beijing
- Agency: Buchanan Ingersoll & Rooney PC
- International Application: PCT/CN2014/092342 WO 20141127
- International Announcement: WO2016/082141 WO 20160602
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10 ; G11C7/10 ; G06F3/06 ; G11C29/52 ; H03M13/29 ; G06F5/10 ; H03M13/05 ; H03M13/19 ; G11C29/04

Abstract:
A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.
Public/Granted literature
- US20160364290A1 CONFIGURATION STRUCTURE AND METHOD OF A BLOCK MEMORY Public/Granted day:2016-12-15
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