Invention Grant
- Patent Title: Chunk redundancy architecture for memory
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Application No.: US13995169Application Date: 2012-03-29
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Publication No.: US09727417B2Publication Date: 2017-08-08
- Inventor: Toru Tanzawa
- Applicant: Toru Tanzawa
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- International Application: PCT/US2012/031247 WO 20120329
- International Announcement: WO2013/147800 WO 20131003
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F3/06 ; G11C29/00

Abstract:
An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.
Public/Granted literature
- US20130332674A1 CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY Public/Granted day:2013-12-12
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