Invention Grant
- Patent Title: Core-specific fuse mechanism for a multi-core die
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Application No.: US15209048Application Date: 2016-07-13
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Publication No.: US09727477B2Publication Date: 2017-08-08
- Inventor: G. Glenn Henry , Dinesh K. Jain
- Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agent Richard K. Huffman; James W. Huffman
- Main IPC: G06F13/12
- IPC: G06F13/12 ; G06F12/0875 ; G11C17/16 ; G06F3/06 ; G06F9/44 ; G06F9/445 ; G06F12/06 ; G06F12/0806 ; G11C17/18 ; G11C29/00 ; G06F11/10 ; G06F12/0802 ; G11C29/52 ; G06F12/128 ; G06F1/24 ; G06F12/084 ; G06F12/0811

Abstract:
An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.
Public/Granted literature
- US20160321004A1 CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE Public/Granted day:2016-11-03
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