Invention Grant
- Patent Title: Tracking memory accesses when invalidating effective address to real address translations
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Application No.: US14727075Application Date: 2015-06-01
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Publication No.: US09727483B2Publication Date: 2017-08-08
- Inventor: Bartholomew Blaner , Jay G. Heaslip , Kenneth A. Lauricella , Jeffrey A. Stuecheli
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Mark G. Edwards
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/1009

Abstract:
According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.
Public/Granted literature
- US20160179698A1 TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS Public/Granted day:2016-06-23
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