Invention Grant
- Patent Title: Delta retiming in logic simulation
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Application No.: US13731604Application Date: 2012-12-31
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Publication No.: US09727668B2Publication Date: 2017-08-08
- Inventor: Sachin Kakkar , John Ries
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Banner & Witcoff, Ltd.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.
Public/Granted literature
- US20130275112A1 DELTA RETIMING IN LOGIC SIMULATION Public/Granted day:2013-10-17
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