For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform invariant node, and the second timing arc generation factors only the uniform waveform. Similarly, a setup arc employs the uniform waveform rather than multiple clock input waveforms in computing setup/hold values. Simulation of waveform propagation is also simplified by simulating only the uniform waveform for the second portion. Additionally, the first arc may be shared between a plurality of circuit paths which share an input pin and the waveform invariant node.