A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first timing details and the second timing details.