Invention Grant
- Patent Title: System and method of training optimization for dual channel memory modules
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Application No.: US15331064Application Date: 2016-10-21
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Publication No.: US09728236B1Publication Date: 2017-08-08
- Inventor: Vadhiraj Sankaranarayanan , Bhyrav M. Mutnury , Stuart Allen Berke
- Applicant: DELL PRODUCTS, LP
- Applicant Address: US TX Round Rock
- Assignee: Dell Products, LP
- Current Assignee: Dell Products, LP
- Current Assignee Address: US TX Round Rock
- Agency: Larson Newman, LLP
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C7/10
Abstract:
A memory channel includes a dual channel double data rate (DDR) memory device having a first bank of memory accessed by a first data bus and a first command/address (C/A) bus, and a second bank of memory accessed by a second data bus and a second C/A bus, and a memory controller configured to train the first and second C/A busses with both the first and second C/A busses active, and to train one of the first and second C/A busses with the other of the first and second C/A busses idle.
Information query
