A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.