- Patent Title: Space-efficient underfilling techniques for electronic assemblies
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Application No.: US15089491Application Date: 2016-04-02
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Publication No.: US09728425B1Publication Date: 2017-08-08
- Inventor: Joshua D. Heppner , Serge Roux , Michael J. Baker , Javier A. Falcon
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/67 ; B29C35/08 ; B29C70/84 ; B29C70/80 ; B29C70/88 ; H01L23/31 ; B29K63/00 ; B29L31/34

Abstract:
Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.
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