Invention Grant
- Patent Title: Method for forming conducting via and damascene structure
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Application No.: US14161258Application Date: 2014-01-22
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Publication No.: US09728445B2Publication Date: 2017-08-08
- Inventor: Wen-Kuo Hsieh , Ming-Chung Liang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/311

Abstract:
In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH2F2 and an auxiliary gas of N2 or O2.
Public/Granted literature
- US20150206792A1 METHOD FOR FORMING CONDUCTING VIA AND DAMASCENE STRUCTURE Public/Granted day:2015-07-23
Information query
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