- Patent Title: Methods for hybrid wafer bonding integrated with CMOS processing
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Application No.: US13903700Application Date: 2013-05-28
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Publication No.: US09728453B2Publication Date: 2017-08-08
- Inventor: Pin-Nan Tseng , Chia-Shiung Tsai , Ping-Yin Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/768 ; H01L23/00

Abstract:
Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.
Public/Granted literature
- US20140273347A1 Methods for Hybrid Wafer Bonding Integrated with CMOS Processing Public/Granted day:2014-09-18
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