Invention Grant
- Patent Title: System with a high power chip and a low power chip having low interconnect parasitics
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Application No.: US13227328Application Date: 2011-09-07
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Publication No.: US09728481B2Publication Date: 2017-08-08
- Inventor: Abraham F. Yee , Joe Greco , Jun Zhai , Joseph Minacapelli , John Y. Chen
- Applicant: Abraham F. Yee , Joe Greco , Jun Zhai , Joseph Minacapelli , John Y. Chen
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: H01L23/10
- IPC: H01L23/10 ; H01L23/36 ; H01L23/498 ; H01L23/538 ; H01L25/065 ; H01L25/18 ; H01L23/31

Abstract:
An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.
Public/Granted literature
- US20130058067A1 SYSTEM WITH A HIGH POWER CHIP AND A LOW POWER CHIP HAVING LOW INTERCONNECT PARASITICS Public/Granted day:2013-03-07
Information query
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