Invention Grant
- Patent Title: Partially biased isolation in semiconductor devices
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Application No.: US14851355Application Date: 2015-09-11
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Publication No.: US09728600B2Publication Date: 2017-08-08
- Inventor: Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L29/10 ; H01L29/66 ; H01L21/22 ; H01L21/768 ; H01L29/36 ; H01L27/02 ; H01L23/528

Abstract:
A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.
Public/Granted literature
- US20170077219A1 PARTIALLY BIASED ISOLATION IN SEMICONDUCTOR DEVICES Public/Granted day:2017-03-16
Information query
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