Invention Grant
- Patent Title: Thin film transistor array panel and conducting structure
-
Application No.: US15071173Application Date: 2016-03-15
-
Publication No.: US09728650B1Publication Date: 2017-08-08
- Inventor: Yi-Chun Kao , Hsin-Hua Lin , Po-Li Shih , Wei-Chih Chang , I-Min Lu , I-Wei Wu
- Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
- Applicant Address: TW New Taipei
- Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee Address: TW New Taipei
- Agent Steven Reiss
- Main IPC: H01L29/45
- IPC: H01L29/45 ; H01L27/12 ; H01L29/786 ; H01L29/24

Abstract:
A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.
Public/Granted literature
- US20170207342A1 THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE Public/Granted day:2017-07-20
Information query
IPC分类: