A fault detection circuit includes a micro processing unit configured to output a first pulse width modulation (PWM) signal, a driver electrically coupled to the micro processing unit, and a comparator configured to electrically connect the micro processing unit and the driver. The first PWM signal is configured to drive the driver to output a second PWM signal configured to drive the electrical device. The comparator is configured to compare the second PWM signal with a reference level to output a third PWM signal to the micro processing unit. The third PWM signal contains a number of high level signals and low level signals. The micro processing unit is configured to detect the number of the high level signals and the number of the low level signals during at least one time period to determine a status of an electrical device.