Power converter includes a switched power stage to generate an output voltage from an input voltage, and a controller to generate a pulse width modulation (PWM) signal for switching the switched power stage in dependence upon a voltage error signal. The voltage error signal is a difference between a reference voltage and the output voltage. The controller comprises a synchronizer to generate a first clock signal for clocking a low frequency domain of the controller, and a digital PWM controller clocked by the first clock signal and configured to determine an on-time information of the PWM signal and a PWM generator to generate the PWM signal based on the on-time information. The synchronizer is configured to synchronize a frequency of the PWM signal to a frequency imposed by the external reference signal by synchronizing a frequency of the first clock signal to the frequency imposed by the external reference signal.