Invention Grant
- Patent Title: Area-delay-power efficient multibit flip-flop
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Application No.: US14682413Application Date: 2015-04-09
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Publication No.: US09729128B2Publication Date: 2017-08-08
- Inventor: Manish Srivastava , Basannagouda Somanath Reddy
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Bever, Hoffman & Harms, LLP
- Main IPC: H03K3/02
- IPC: H03K3/02 ; H03K3/012 ; H03K5/24 ; H03K3/3562

Abstract:
A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.
Public/Granted literature
- US20160301391A1 Area-Delay-Power Efficient Multibit Flip-Flop Public/Granted day:2016-10-13
Information query
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