Invention Grant
- Patent Title: System and method for reducing metastability in CMOS flip-flops
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Application No.: US14631867Application Date: 2015-02-26
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Publication No.: US09729129B2Publication Date: 2017-08-08
- Inventor: Bhaskar Gopalan
- Applicant: Bhaskar Gopalan
- Agency: Patent 360 LLC
- Agent Barry Choobin
- Main IPC: H03K3/037
- IPC: H03K3/037

Abstract:
A circuit and method for reducing metastability of a CMOS SR flip flop is provided. The circuit comprises a first switching module and a second switching module that are operatively coupled to a first and second output terminal of the CMOS SR flip-flop. The method includes injecting current onto the first and second output terminals of the CMOS SR flip-flop at mutually opposite directions during permissible mid-range voltages of the output terminals. Further, the method includes driving the output terminals of the CMOS SR flip-flop into the predetermined state of zero and predetermined stable state of Vdd by utilizing the currents injected onto the output terminals. As a result, the metastable point of the CMOS flip-flop is diverted from the corresponding metastable voltage and thereby reduces the metastability of the CMOS SR flip-flop.
Public/Granted literature
- US20160164502A1 SYSTEM AND METHOD FOR REDUCING METASTABILITY IN CMOS FLIP-FLOPS Public/Granted day:2016-06-09
Information query
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